performance & reliability of 3d architectures (pi fet, finfet, omega fet)
| Description | |
| Date | 2018 |
| Date | |
| Auteurs | Laurent,- A | Garros,- X | Barraud,- S | Pelloux-prayer,- J | Casse,- M | Gaillard,- F | Federspiel,- X | Roy,- D | Vincent,- E | Ghibaudo,- G | |
| Source | 2018 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) 2018, pages: 6 |
| Résumé | "The impact of 3D architectures and boosters on the trade-off performance/reliability is deeply investigated in this paper. ""Finfet"" transistor presents a slight superior trade-off than square shaped ""Pi fet"" device because of little improved performance and similar BTI&HC reliability. ""Omega fet"" also offers a better compromise than Met due to improved BTI reliability. Finally strained SOI & SiGeOI devices are highly suitable since they allow boosting the transistor performance without any reliability penalty." |
| DOI | |
| Type de documents | |
| Impact Factor | |